The present invention relates to technique of performing high speed processing of a large quantity of data, such as image processing of a camera and high-speed data transmission, and especially relates to a microcomputer, a system including the microcomputer, and a data transfer device, in which plural pieces of prescribed data are extracted from data of a processing object, and are transferred to respectively different areas in a memory.
In recent years, demands of high speed processing of a large quantity of data are growing in a technical field of image processing, etc. For example, in performing arithmetic processing to an image captured by a camera and displaying the image after the arithmetic processing, it is desirable to process a large quantity of data at high speed, when real time nature is required. Inventions disclosed by following Patent Literatures 1-4 describe technique relevant to the matter.
An invention disclosed by Patent Literature 1 relates to a display driving circuit aiming at writing plural pieces of data, even when an external selection signal does not change. Display data from the exterior is loaded into a shift register via a CCB interface. According to a display data transfer counted by a serial data counter, the display data is sequentially written in a DCRAM or an ADRAM.
An invention disclosed by Patent Literature 2 aims at realization of high-speed decompressing of compressed data and high-speed data transfer to a fluid injection head, and also aims at striking acceleration of an execution speed of fluid injection of a fluid injector as compared with the past. Record control data received by an interface unit is transferred to a switching control block, and to a header analysis block to conduct analysis of a header. When data succeeding the header is a command, the command is stored in a command storing register, and when the data is compressed record data, the data is transferred to a data transfer control block. An MPU accesses the command storing register and conducts a command analysis. Compressed record data is stored in a FIFO memory via a first dedicated bus from the data transfer control block, and is transferred to a DECU via a second dedicated bus.
An invention disclosed by Patent Literature 3 aims at dealing with different kinds of serial data by one serial interface circuit. A selector circuit is arranged on one side or both sides of plural transmitting/receiving FIFOs, and the number of allocation and coupling method of the FIFOs to a serial input/output circuit are changed by switching of the selector circuit.
An invention disclosed by Patent Literature 4 relates to a multiinput circuit of a switch signal, aiming at reduction of the number of in-use terminal of a parallel interface, and allowing a data input of many switches. The multiinput circuit is comprised of a parallel interface, a CPU, and plural hexadecimal switches. A common data bus and a data output enabling signal line of the switches couple the interface and the switches. A data output switch is selected by a data output enabling signal, and data is inputted using the common data bus. Accordingly, the number of in-use terminal of the parallel interface is reduced.    Patent Literature 1: Japanese Unexamined Patent Publication No. 2002-297080    Patent Literature 2: Japanese Unexamined Patent Publication No. 2005-28875    Patent Literature 3: Japanese Unexamined Patent Publication No. 2002-91904    Patent Literature 4: Japanese Unexamined Patent Publication No. Hei 5(1993)-127788